Last Updated on 2026 年 3 月 30 日 by 総合編集組
Essential Keywords for Glass Substrates in Semiconductor Packaging: CTE 3-6 ppm/°C, TGV Aspect Ratio 15:1, L/S 2-5μm, and Global Competition Analysis
Introduction The semiconductor industry is undergoing a significant transition in advanced packaging as artificial intelligence (AI) and high-performance computing (HPC) demands continue to surge. Traditional organic substrates, such as those based on Ajinomoto Build-up Film (ABF), are reaching physical limits in handling ultra-large packages, high wiring density, and stringent thermal management. Glass substrates emerge as a promising next-generation solution due to their superior mechanical strength, thermal stability, and electrical performance. This summary highlights key technical terms, physical advantages, manufacturing processes, product categories, industry competition, market trends, and future outlook based on comprehensive technical insights.
Why the Shift to Glass Substrates? In semiconductor packaging history, substrates have played a critical role in supporting chips, providing electrical connections, and aiding heat dissipation. For decades, the industry relied on organic substrates made from plastic resins and fibers. However, as generative AI models scale toward trillions of parameters, processor power often exceeds 1000 watts. This creates severe bottlenecks due to the mismatch in coefficient of thermal expansion (CTE) between organic materials and silicon dies.
Organic substrates suffer from high CTE values (typically 10-17 ppm/°C), leading to significant warpage—often called “potato-chipping”—under high temperatures. This warpage causes solder bump cracking and restricts package sizes beyond 55 mm. Surface roughness also limits fine line/space (L/S) features below 1.5 μm, hindering bandwidth in chiplet architectures. Glass substrates address these issues with tunable CTE close to silicon (3-6 ppm/°C), exceptional flatness, and low surface roughness (<1 nm), enabling larger, more reliable packages.
Core Physical Advantages: A Detailed Comparison Glass substrates offer clear superiority across multiple metrics. Key indicators include:
- CTE (ppm/°C): Organic (10-17) vs. Glass (3-6) vs. Silicon (2.5-3) — Glass closely matches silicon, minimizing stress during thermal cycling.
- Dielectric Loss Tangent (@10 GHz): Organic (>0.01) vs. Glass (<0.002) — Extremely low loss supports high-frequency signal integrity up to 100 GHz.
- Flatness/Warpage (over 100 mm): Organic (>50 μm) vs. Glass (<20 μm) — Superior planarity for advanced lithography.
- Surface Roughness (nm): Organic (higher) vs. Glass (<1) — Enables finer patterning.
- Moisture Absorption: Organic (absorbs, affecting electrical properties) vs. Glass (none) — Higher long-term reliability.
- Supported L/S (μm): Organic (8-15) vs. Glass (2-5) — Allows denser interconnects for chiplet designs.
These properties make glass ideal for rigid, thin-form designs while maintaining dimensional stability. High stiffness further prevents deformation in large-scale heterogeneous integration.
Through Glass Via (TGV) Technology: The Vertical Interconnect Bridge The cornerstone of glass substrate competitiveness is Through Glass Via (TGV) technology, which creates microscopic vertical channels for front-to-back electrical connections. Several formation methods exist:
- Laser Drilling: Fast and flexible but may introduce micro-cracks and heat-affected zones on via walls.
- Laser Induced Deep Etching (LIDE): A breakthrough process involving laser modification of glass structure followed by selective wet etching. It achieves aspect ratios exceeding 15:1 with smooth walls and minimal cracking.
- Plasma Etching: Provides uniform via control through anisotropic plasma but is less efficient for thick glass, requiring precise bias voltage (100-300V).
Post-formation, metallization fills vias with copper. Two main approaches:
- Full Filling Type: Completely fills the via for optimal electrical and thermal performance, though slower.
- Conformal Type: Plates only sidewalls, reducing stress mismatch but with lower current capacity.
Optimized TGV processes deliver 1-2 dB lower signal loss at 10 GHz compared to silicon through-silicon vias (TSV), with via-to-via crosstalk reduced by over two times due to glass’s low dielectric constant.
Product Classification and Application Scenarios Glass substrates form a diverse family:
- Carrier Glass: Temporary support in wafer-level or panel-level packaging, leveraging high transparency for efficient laser debonding.
- Glass Core Substrate: Replaces organic core for exceptional rigidity, supporting over 12 layers of high-bandwidth memory (HBM) and large logic dies in heterogeneous integration.
- Glass Interposer: Cost-effective alternative to silicon interposers for large-area, high-frequency signal bridging in AI accelerators and network switches.
Applications span:
- AI Accelerators / HPC: Ultra-large packages with trillion-transistor integration, solving warpage in massive modules.
- RF and 5G/6G: Ultra-low dielectric loss for signal purity up to 100 GHz.
- Co-Packaged Optics (CPO): Natural transparency enables direct embedding of optical waveguides and fiber coupling.
- High-Bandwidth Memory (HBM): High-density I/O via TGV combined with thermal vias for better heat management.
Global Competitive Landscape The commercialization race involves IDMs, OSATs, and glass material giants. Intel leads with over a decade of research, demonstrating glass-core test chips and planning processors with embedded multi-die interconnect bridge (EMIB) targeting one trillion transistors by 2030. The company explores patent licensing to accelerate ecosystem growth.
Samsung integrates display and memory expertise, aiming for volume production in late 2026 focused on AI ASICs. SKC’s subsidiary Absolics established the world’s first dedicated glass substrate fab in Georgia, USA, partnering with AMD and AWS while receiving CHIPS Act support as a third-party supplier.
Material leaders include:
- Corning: Precision glass with tunable CTE (3.2-12.4 ppm/°C) via fusion draw process for ultra-flat surfaces.
- NEG: GC Core® microcrystalline glass combining electrical properties with ceramic-like strength and efficient CO₂ laser processing.
- AGC: Leading market share with consistent large panels (510 mm × 515 mm) from display heritage.
Market Trends and Regional Insights The glass substrate TGV market was valued at approximately 8.6 billion USD in 2024, projected to reach 15.54 billion USD by 2034 at a CAGR of 8.9%. Growth accelerates in premium AI/HPC segments. Asia-Pacific dominates due to strong supply chains, while North America drives innovation via design leaders like NVIDIA, AMD, and Intel. Europe benefits from automotive electronics and research institutions such as IMEC. Glass substrates are expected to capture 20-30% of advanced packaging share by 2036, especially in high-value server chips.
Community Discussions: Enthusiasm and Concerns Tech communities show polarized views. Positive feedback highlights paradigm shifts enabling 40% performance gains and 50% power reduction, supporting trillion-parameter models. Critics raise brittleness risks during CPU installation, potential thermal misconceptions (addressed by dense copper thermal vias), and higher initial costs (2-3 times organic substrates) that may raise end-product prices.
Implementation Challenges and Future Roadmap Key hurdles include yield rates (75-85% vs. >95% for organic), need for specialized handling equipment, CTE mismatch between glass and copper (17 ppm/°C) causing interface stress, and the requirement for new EDA tools and reliability standards tailored to glass’s rigidity and fracture behavior.
The 2027-2030 period marks the transition: enabling super-large heterogeneous integration with over 16 HBM4 stacks, co-packaged optics via laser-written waveguides, and cost reduction through panel-level manufacturing from display lines. This will extend glass adoption to mainstream high-end consumer electronics.
Conclusion Glass substrates represent an inevitable evolution for overcoming AI compute bottlenecks. By solving organic warpage, enabling dense interconnects, and supporting photonic integration, this ancient material is redefining modern computing brains. Stakeholders should monitor TGV yield improvements and standardization as commercialization inflection points. While challenges remain, collaborative efforts from Intel, Samsung, SKC, and glass giants are rapidly moving the technology from labs to data centers.
